1. Field of the Invention
The present invention relates generally to semiconductor manufacturing and, more particularly, to zero-order overlay targets.
2. Description of Related Art
Semiconductor manufacturing generally involves the formation of several layers of different materials on top of each other. For example, features such as transistor gates and interconnects are created within separate layers of the same integrated circuit, and thus require distinct lithography steps. Typically, the alignment tolerance of these layers is less than the width of a single gate.
The term “overlay” generally refers to the displacement of a layer from its ideal position with respect to a lower layer. In most instances, the overlay may be represented by a two dimensional vector in the plane of the semiconductor wafer. The goal of overlay metrology is to determine and correct overlay errors, thus providing structures that have approximately perfect overlay or alignment.